CONFIGURABLE LOW VOLTAGE DETECTION THRESHOLD AT A MEMORY SYSTEM
개요
발명자
Caixia Yang; Deping He
IPC 분류
CPC 분류
Methods, systems, and devices for configurable low voltage detection threshold at a memory system are described. The described techniques provide for a memory system to adjust a low voltage detection (LVD) threshold according to an interface speed of the memory system. The LVD threshold may be correlated with the interface speed, such that when operating at a relatively high interface speed, the memory system may set the LVD threshold to a relatively high value and when operating at a relatively low interface speed, the memory system may set the LVD threshold to a relatively low value. Additionally, or alternatively, the memory system may be configured to adjust the LVD threshold when changing an interface speed for subsequent operations. For example, the memory system may receive a command indicating a second interface speed and may set the LVD threshold to a second value that is associated with the second speed.
원문 (중국어)
Methods, systems, and devices for configurable low voltage detection threshold at a memory system are described. The described techniques provide for a memory system to adjust a low voltage detection (LVD) threshold according to an interface speed of the memory system. The LVD threshold may be correlated with the interface speed, such that when operating at a relatively high interface speed, the memory system may set the LVD threshold to a relatively high value and when operating at a relatively low interface speed, the memory system may set the LVD threshold to a relatively low value. Additionally, or alternatively, the memory system may be configured to adjust the LVD threshold when changing an interface speed for subsequent operations. For example, the memory system may receive a command indicating a second interface speed and may set the LVD threshold to a second value that is associated with the second speed.