PACKAGE STRUCTURE AND PREPARATION METHOD THEREOF
개요
발명자
Haijie CHEN; Jielei XIE
IPC 분류
CPC 분류
A package structure and a related preparation method thereof are disclosed. The package structure includes: an interposer; and a logic chip structure and a signal channel structure that are located on a surface of the interposer, where the logic chip structure includes a logic chip on a surface of the interposer and a power supply channel structure on a surface of the logic chip. A power supply layer of the logic chip is close to the power supply channel structure, which is electrically connected to a corresponding conductive structure to achieve power supply. A signal layer of the logic chip is close to the interposer and connected to the corresponding conductive structure to realize signal transmission. In this way, the power supply does not interfere with signals, and a logic error is avoided; and an overall voltage and power consumption of a finished package is significantly reduced.
원문 (중국어)
A package structure and a related preparation method thereof are disclosed. The package structure includes: an interposer; and a logic chip structure and a signal channel structure that are located on a surface of the interposer, where the logic chip structure includes a logic chip on a surface of the interposer and a power supply channel structure on a surface of the logic chip. A power supply layer of the logic chip is close to the power supply channel structure, which is electrically connected to a corresponding conductive structure to achieve power supply. A signal layer of the logic chip is close to the interposer and connected to the corresponding conductive structure to realize signal transmission. In this way, the power supply does not interfere with signals, and a logic error is avoided; and an overall voltage and power consumption of a finished package is significantly reduced.