RESONANT CLOCKING ARCHITECTURE
개요
발명자
Ragh Kuttappa; Vinayak Honkote; Gaurav Kamalkar; Amreesh Rao; Eric Finley; Kailash Chandrashekar; Jainaveen Sundaram Priya; Tanay Karnik; Stephen Morein; Dileep Kurian; Satish Yada; Srivatsa RS; Patrick Morrow; Paul Fischer; Zhiguo Qian; Adel A. Elsherbini
IPC 분류
CPC 분류
A rotary oscillator array (ROA) apparatus includes a plurality of rotary traveling wave oscillators (RTWOs) configured to generate a plurality of resonant clock signals. An RTWO of the plurality of RTWOs includes a plurality of inverter cells and a fractional divider. The inverter cells are coupled in parallel to each other between two metal interconnects. The fractional divider is coupled to the two metal interconnects. The fractional divider will output a resonant clock signal of the plurality of resonant clock signals based on a reset-out signal generated by a reset-out terminal of the RTWO.
원문 (중국어)
A rotary oscillator array (ROA) apparatus includes a plurality of rotary traveling wave oscillators (RTWOs) configured to generate a plurality of resonant clock signals. An RTWO of the plurality of RTWOs includes a plurality of inverter cells and a fractional divider. The inverter cells are coupled in parallel to each other between two metal interconnects. The fractional divider is coupled to the two metal interconnects. The fractional divider will output a resonant clock signal of the plurality of resonant clock signals based on a reset-out signal generated by a reset-out terminal of the RTWO.