CLOCKING SYSTEM FOR A SYSTEM ON CHIP USING PLL
개요
출원인
Microsoft Technology Licensing, LLC
발명자
Charles Walter BOECKER; Eric Douglas GROEN; Subramanian KRISHNAMOORTHY; Shaishav Achyut DESAI; Gurupada MANDAL; Ravi SHIVNARAINE; Jaskarn S. JOHAL
IPC 분류
CPC 분류
The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.
원문 (중국어)
The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.