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기록

COMMUNICATION CIRCUITS INCLUDING A DIFFERENTIAL TO QUADRATURE PHASE GENERATOR

발명심사 중
2조회수
20청구항 · 3 독립항
§ Ⅰ

개요

발명자

Wei Shuo LIN

IPC 분류

H4L 7/H3K 5/H3L 7/81H4L 7/33

CPC 분류

H4L7/25H3K5/H3L7/814H4L7/337H3K2005/52

A device includes a transmission clock circuit that includes a phase interpolator circuit and a transmission differential to quadrature phase generator. The phase interpolator circuit interpolates phases and provides phase interpolated first clock signals and phase interpolated second clock signals. The transmission differential to quadrature phase generator, duty cycle corrects each of the phase interpolated first clock signals and the phase interpolated second clock signals, quadrature error corrects each of the duty cycle corrected phase interpolated first clock signals and the duty cycle corrected phase interpolated second clock signals, outputs transmission clock signals based on the quadrature error corrected duty cycle corrected phase interpolated first clock signals, and outputs multiple clock phases and a track signal based on the quadrature error corrected duty cycle corrected phase interpolated second clock signals.

원문 (중국어)

A device includes a transmission clock circuit that includes a phase interpolator circuit and a transmission differential to quadrature phase generator. The phase interpolator circuit interpolates phases and provides phase interpolated first clock signals and phase interpolated second clock signals. The transmission differential to quadrature phase generator, duty cycle corrects each of the phase interpolated first clock signals and the phase interpolated second clock signals, quadrature error corrects each of the duty cycle corrected phase interpolated first clock signals and the duty cycle corrected phase interpolated second clock signals, outputs transmission clock signals based on the quadrature error corrected duty cycle corrected phase interpolated first clock signals, and outputs multiple clock phases and a track signal based on the quadrature error corrected duty cycle corrected phase interpolated second clock signals.