SEMICONDUCTOR PACKAGE WITH A CAVITY SUBSTRATE
개요
발명자
Roel ROBLES; Cassandra COSTELO; Roderick RAMIRO; Dennis REYES; Erwin Paul SELLORIQUEZ; Kin Ming LEUNG
IPC 분류
CPC 분류
A semiconductor component package utilizing a cavity substrate is disclosed. The package effectively connects terminals of the semiconductor component to substrate pads on the semiconductor surface within the cavity using a solder preform. The solder preform is configured to fit the semiconductor component within a preform cavity. The solder preform is positioned over the pads on the cavity substrate and reflowed, forming interconnections between the semiconductor component terminals and the substrate pads. In addition, solder fillets are formed surrounding the semiconductor terminal to advantageously increase the strength of the interconnections, providing a more reliable semiconductor component package.
원문 (중국어)
A semiconductor component package utilizing a cavity substrate is disclosed. The package effectively connects terminals of the semiconductor component to substrate pads on the semiconductor surface within the cavity using a solder preform. The solder preform is configured to fit the semiconductor component within a preform cavity. The solder preform is positioned over the pads on the cavity substrate and reflowed, forming interconnections between the semiconductor component terminals and the substrate pads. In addition, solder fillets are formed surrounding the semiconductor terminal to advantageously increase the strength of the interconnections, providing a more reliable semiconductor component package.