CNIPA.AI
검색으로 돌아가기
기록

SEMICONDUCTOR MEMORY DEVICE

발명심사 중
2조회수
20청구항 · 3 독립항
§ Ⅰ

개요

발명자

Jeongsu KIM; Jinwoo HAN

IPC 분류

H10B 12/H1L 23/H1L 25/18H10D 80/30

CPC 분류

H10B12/50H1L24/8H1L25/18H10B12/312H10D80/30H1L2224/8145H1L2924/1436

A semiconductor memory device includes a memory cell array structure, the memory cell array structure comprising a cell substrate layer, a cell array element layer on the cell substrate layer, the cell array element layer including a cell transistor and a cell capacitor, and a cell bonding layer on the cell array element layer, a peripheral circuit structure stacked on the memory cell array structure, and the peripheral circuit structure comprising a peripheral epi layer, the peripheral epi layer having an upper surface facing an upward or downward direction, a peripheral circuit element layer on the peripheral epi layer, the peripheral circuit element layer including a peripheral transistor, an etch stopping layer on a lower surface of the peripheral epi layer, and a peripheral bonding layer bonded to the cell bonding layer.

원문 (중국어)

A semiconductor memory device includes a memory cell array structure, the memory cell array structure comprising a cell substrate layer, a cell array element layer on the cell substrate layer, the cell array element layer including a cell transistor and a cell capacitor, and a cell bonding layer on the cell array element layer, a peripheral circuit structure stacked on the memory cell array structure, and the peripheral circuit structure comprising a peripheral epi layer, the peripheral epi layer having an upper surface facing an upward or downward direction, a peripheral circuit element layer on the peripheral epi layer, the peripheral circuit element layer including a peripheral transistor, an etch stopping layer on a lower surface of the peripheral epi layer, and a peripheral bonding layer bonded to the cell bonding layer.