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기록

METHODS OF MANUFACTURING 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH ELECTRONIC CIRCUIT UNITS

발명심사 중
20청구항 · 3 독립항
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개요

발명자

Zvi Or-Bach; Jin-Woo Han; Brian Cronquist

IPC 분류

H10B 80/H1L 23/H1L 23/498H1L 23/538H1L 25/H1L 25/16H10B 10/H10B 99/H10D 80/20H10D 88/

CPC 분류

H10B80/H1L23/49827H1L23/5384H1L24/5H1L24/8H1L25/16H1L25/50H10B10/18H10B99/14H10B99/22H10D80/215H10D80/251H10D88/1H1L2224/5073H1L2224/5548H1L2224/5573H1L2224/8238H1L2924/1205H1L2924/1304H1L2924/1432H1L2924/1437

A method of manufacturing a 3D device including: forming a first level including first transistors and a first interconnect; forming a second level including second transistors; overlaying the second level on the first level; and bonding the second level to the first level; the bonding includes performing metal region to metal region bonding, the 3D device includes at least four electronic circuits (AL4ECs) and at least one redundancy circuit, where the AL4ECs each include a first circuit which includes a portion of the first transistors, where the AL4ECs include a second circuit which includes a portion of the second transistors, where the AL4ECs each include a vertical connectivity structure (VCSt), the VCSt includes pillars, where the pillars are configured to provide electrical connections between the first circuit and the second circuit, and where the AL4ECs each include at least one memory control circuit and at least one memory array.

원문 (중국어)

A method of manufacturing a 3D device including: forming a first level including first transistors and a first interconnect; forming a second level including second transistors; overlaying the second level on the first level; and bonding the second level to the first level; the bonding includes performing metal region to metal region bonding, the 3D device includes at least four electronic circuits (AL4ECs) and at least one redundancy circuit, where the AL4ECs each include a first circuit which includes a portion of the first transistors, where the AL4ECs include a second circuit which includes a portion of the second transistors, where the AL4ECs each include a vertical connectivity structure (VCSt), the VCSt includes pillars, where the pillars are configured to provide electrical connections between the first circuit and the second circuit, and where the AL4ECs each include at least one memory control circuit and at least one memory array.