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기록

SHALLOW-TRENCH ISOLATION PROTECTION STRUCTURE FOR NANOSTRUCTURE FIELD-EFFECT TRANSISTOR DEVICE AND METHODS OF FORMING

발명심사 중
20청구항 · 3 독립항
§ Ⅰ

개요

발명자

Fang Hsuan Hu; Zhen-Cheng Wu; Yen-Chun Huang; Tze-Liang Lee

IPC 분류

H10D 30/1H10D 30/

CPC 분류

H10D30/19H10D30/501

A shallow trench isolation (STI) protection structure is formed on the STI regions of a nanostructure field-effect transistor (NSFET) device. The STI protection structure protects the STI regions during a subsequent selective etching process for removing a disposable material used in a disposable oxide interposer (DOI) process for forming the NSFET device. The STI protection structure may include a single hard mask layer with high etching resistance to the selective etching process. Alternatively, the STI protection structure may have a dual-layered or tri-layered structure with different materials in each sublayer of the STI protection structure. Area-selective atomic layer deposition (AS-ALD) is used to form the STI protection structure such that the STI protection structure is selectively formed on the upper surface of the STI regions.

원문 (중국어)

A shallow trench isolation (STI) protection structure is formed on the STI regions of a nanostructure field-effect transistor (NSFET) device. The STI protection structure protects the STI regions during a subsequent selective etching process for removing a disposable material used in a disposable oxide interposer (DOI) process for forming the NSFET device. The STI protection structure may include a single hard mask layer with high etching resistance to the selective etching process. Alternatively, the STI protection structure may have a dual-layered or tri-layered structure with different materials in each sublayer of the STI protection structure. Area-selective atomic layer deposition (AS-ALD) is used to form the STI protection structure such that the STI protection structure is selectively formed on the upper surface of the STI regions.