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기록

METHOD TO PRODUCE A 3D MULTILAYER SEMICONDUCTOR DEVICE AND STRUCTURE

발명심사 중
2조회수
20청구항 · 3 독립항
§ Ⅰ

개요

발명자

Zvi Or-Bach; Jin-Woo Han

IPC 분류

H10D 30/1H1L 21/2H1L 21/308H1L 21/768H1L 23/H10B 41/23H10B 41/35H10B 43/23H10B 43/35H10D 30/68H10D 30/69H10D 62/832

CPC 분류

H10D30/411H1L21/2532H1L21/2598H1L21/308H1L21/76898H1L24/8H1L24/80H10B41/23H10B41/35H10B43/23H10B43/35H10D30/413H10D62/832H1L2224/8145H1L2224/80201H1L2924/14511H10D30/689H10D30/693

Methods of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer (SCSL); providing a second substrate including a second level, the second level including a second SCSL; performing an epitaxial growth of a SiGe layer on top of the second SCSL; performing an epitaxial growth of a third SCSL on top of the SiGe layer, the third SCSL has an average thickness of less than 2,000 nm; forming second transistors each including a single crystal channel, where forming the second transistors includes growth of a second SiGe layer on top of the third SCSL; forming many metal layers interconnecting the second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL.

원문 (중국어)

Methods of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer (SCSL); providing a second substrate including a second level, the second level including a second SCSL; performing an epitaxial growth of a SiGe layer on top of the second SCSL; performing an epitaxial growth of a third SCSL on top of the SiGe layer, the third SCSL has an average thickness of less than 2,000 nm; forming second transistors each including a single crystal channel, where forming the second transistors includes growth of a second SiGe layer on top of the third SCSL; forming many metal layers interconnecting the second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL.