THIN FILM TRANSISTORS HAVING RECESSED CONTACT METALLIZATION
개요
발명자
Moshe DOLEJSI; Vishak VENKATRAMAN; Deepyanti TANEJA; Van H. LE; Travis W. LAJOIE; Suraj MATHEW; Abhishek Anil SHARMA; Christopher J. WIEGAND; Gregory J. GEORGE; Taniya KEKUNAWELA PATHIRANAGE; Juichin ALCANTARA; Shardul WADEKAR; Philip E. HEIL; Yu-Wen HUANG; Nikhil MEHTA; Joel M. STETTLER
IPC 분류
CPC 분류
Thin film transistors are described. An integrated circuit structure includes a gate electrode. A gate dielectric layer is on the gate electrode. A channel material layer is on the gate dielectric layer. A dielectric layer is over the channel material layer. Source or drain contacts are on the channel material layer. Each of the source or drain contacts includes a semiconductor material layer, a conductive liner within the semiconductor material layer, and a conductive fill within the conductive liner. One, two or all three of the semiconductor material layer, the conductive liner, or the conductive fill has an uppermost surface below an uppermost surface of the dielectric layer.
원문 (중국어)
Thin film transistors are described. An integrated circuit structure includes a gate electrode. A gate dielectric layer is on the gate electrode. A channel material layer is on the gate dielectric layer. A dielectric layer is over the channel material layer. Source or drain contacts are on the channel material layer. Each of the source or drain contacts includes a semiconductor material layer, a conductive liner within the semiconductor material layer, and a conductive fill within the conductive liner. One, two or all three of the semiconductor material layer, the conductive liner, or the conductive fill has an uppermost surface below an uppermost surface of the dielectric layer.