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기록

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SELECTIVELY GROWN METAL GATE STRUCTURES

발명심사 중
2조회수
20청구항 · 3 독립항
§ Ⅰ

개요

발명자

Guowei XU; Chia-Ching LIN; Tao CHU; Kan ZHANG; Lin HU; Yang ZHANG; Robin CHAO; Ting-Hsiang HUNG; Feng ZHANG; Chun Wing YEUNG; Chung-Hsun LIN; Oleg GOLONZKA; Anand S. MURTHY

IPC 분류

H1L 29/423H1L 21/8238H1L 27/6H1L 27/92H1L 29/6H1L 29/8H1L 29/66H1L 29/775H1L 29/786

CPC 분류

H10D30/6735H10D30/14H10D30/43H10D30/6757H10D62/121H10D62/151H10D64/17H10D84/167H10D84/172H10D84/38H10D84/85H10D88/

Integrated circuit structures having selectively grown metal gate structures are described. For example, a structure includes a first vertical arrangement of horizontal nanowires or fin laterally spaced apart from a second vertical arrangement of horizontal nanowires or fin. A first gate stack is over the first vertical arrangement of horizontal nanowires or fin, the first gate stack having a first conductive layer over a first gate dielectric, and a first conductive fill over the first conductive layer. A second gate stack is over the second vertical arrangement of horizontal nanowires or fin, the second gate stack having a second conductive layer over a second gate dielectric, and a second conductive fill over the second conductive layer and over the first conductive fill. A portion of the second conductive fill is laterally adjacent to the first conductive fill without having the second conductive layer there between.

원문 (중국어)

Integrated circuit structures having selectively grown metal gate structures are described. For example, a structure includes a first vertical arrangement of horizontal nanowires or fin laterally spaced apart from a second vertical arrangement of horizontal nanowires or fin. A first gate stack is over the first vertical arrangement of horizontal nanowires or fin, the first gate stack having a first conductive layer over a first gate dielectric, and a first conductive fill over the first conductive layer. A second gate stack is over the second vertical arrangement of horizontal nanowires or fin, the second gate stack having a second conductive layer over a second gate dielectric, and a second conductive fill over the second conductive layer and over the first conductive fill. A portion of the second conductive fill is laterally adjacent to the first conductive fill without having the second conductive layer there between.