WRAP AROUND CONTACT WITH SELF-ALIGNED GATE ISOLATION

원문 (중국어)

Semiconductor devices with self-aligned gate isolation and wrap around source/drain contacts are provided. In one aspect, a semiconductor device includes: at least a first FET (FET1) and a second FET (FET2), adjacent to one another on a wafer; a dielectric bar between gates of the FET1 and the FET2, and between source/drain regions of the FET1 and the FET2; and wrap around source/drain contacts that at least partially surround the source/drain regions of the FET1 and the FET2. A shallow trench isolation (STI) region can be present between the FET1 and the FET2 and the dielectric bar can be centered over, and directly contact the STI region. Portions of the dielectric bar between the gates and between the source/drain regions can have a height H1 and H2, respectively, where H1>H2. A method of fabricating the present semiconductor device is also provided.