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기록

GATE-ALL-AROUND DEVICES WITH INNER SPACER AND CHANNEL THICKNESS MODULATION

발명심사 중
3조회수
20청구항 · 3 독립항
§ Ⅰ

개요

발명자

Shao-Ming Koh; Nick Lindert; Ramy Ghostine; Li Huey Tan; Vivek Thirtha; Vishal Tiwari; Tao Chu; Marvin Y. Paik

IPC 분류

H1L 27/92H1L 21/8238H1L 29/6H1L 29/423H1L 29/66H1L 29/775H1L 29/786

CPC 분류

H10D84/856H10D30/14H10D30/43H10D30/6735H10D30/6757H10D62/121H10D64/17H10D64/18H10D84/167H10D84/184H10D84/38

Techniques are provided to form semiconductor devices with different inner spacer widths and different nanoribbon (e.g., or nanowire, or nanosheet) thickness. In an example, any number of first semiconductor devices include first gate structures around first semiconductor regions and any number of second semiconductor devices include second gate structures around second semiconductor regions. First dielectric inner spacers are provided between the first gate structure and the corresponding source or drain regions of the first semiconductor devices with a first width and second dielectric inner spacers are provided between the second gate structure and the corresponding source or drain regions of the second semiconductor devices with a second width that is greater than the first width. In some such examples, the first semiconductor regions may be thinner compared to the second semiconductor regions to cause a corresponding increase in the threshold voltage of the first semiconductor devices.

원문 (중국어)

Techniques are provided to form semiconductor devices with different inner spacer widths and different nanoribbon (e.g., or nanowire, or nanosheet) thickness. In an example, any number of first semiconductor devices include first gate structures around first semiconductor regions and any number of second semiconductor devices include second gate structures around second semiconductor regions. First dielectric inner spacers are provided between the first gate structure and the corresponding source or drain regions of the first semiconductor devices with a first width and second dielectric inner spacers are provided between the second gate structure and the corresponding source or drain regions of the second semiconductor devices with a second width that is greater than the first width. In some such examples, the first semiconductor regions may be thinner compared to the second semiconductor regions to cause a corresponding increase in the threshold voltage of the first semiconductor devices.