Chip aging method and device
데이터 출처: EPO OPS
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개요
출원 번호
CN202310261232
발명자
JIAO HUIFANG; WAN JUN; ZHU GUOLIANG; DONG WEI; ZHOU XUE
출원일
Mar 13, 2023
공개일
Sep 13, 2024
특허 패밀리 ID
92659900
IPC 분류
CPC 분류
The invention discloses a chip aging method and device, the aging device is connected with a driving circuit of a chip, and the driving circuit comprises a phase inverter and at least one selection transistor; the device is connected with an input end of a phase inverter and a grid electrode of a selection transistor, an output end of the phase inverter is connected with a drain electrode of the selection transistor, and a source electrode of the selection transistor and a second power supply end of the phase inverter are connected with low voltage; a high voltage is connected to a first power supply end of the phase inverter. The method comprises the following steps: outputting a first level for forming a direct-current electric field between input and output of the phase inverter to the phase inverter; or outputting a second level for controlling the conduction of the first power supply end and the output end to the phase inverter, and outputting a third level for forming a direct-current electric field between the source electrode and the drain electrode of the selection transistor to the grid electrode of the selection transistor, so that the driving circuit with the quality problem fails after accelerated aging; and row or multi-row failure of the chip caused by medium time-dependent breakdown or hot carrier degradation of the driving circuit after leaving a factory is avoided.
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