Packaging structure and preparation method thereof, circuit board and electronic equipment
데이터 출처: EPO OPS
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개요
출원 번호
CN202411111996
발명자
ZHOU WEI; CUI MENGHUA; WANG ZUKUN; ZHANG SHIYOU
출원일
Aug 14, 2024
공개일
Sep 13, 2024
특허 패밀리 ID
92670353
IPC 분류
CPC 분류
[0001] This application relates to a packaging structure and its fabrication method, as well as a circuit board and electronic device. The packaging structure includes a stacked structure, which includes a dielectric layer, comprising a first dielectric layer and a second dielectric layer. At least one side of the first dielectric layer is provided with a second dielectric layer, and a power device is embedded in the first dielectric layer. This packaging structure not only eliminates the need for a casing and sealant, improving integration, but also, to a certain extent, prevents heat generated by the power device from being transferred to at least one surface of the packaging structure, mitigating the thermal impact of the power device on other components on the corresponding surface of the packaging structure during operation.
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