Semiconductor device packaging structure and electronic equipment

The utility model provides a semiconductor device packaging structure and electronic equipment. Relates to the technical field of semiconductor device manufacturing. The semiconductor device packaging structure comprises a multi-lamination substrate, an active layer and a first colloid, the multi-laminated substrate comprises a top layer substrate and a bottom layer substrate, and other layer structures, such as an oxidation buried layer, can be stacked between the top layer substrate and the bottom layer substrate; the side surface of the multi-laminated substrate is provided with a groove which is recessed towards the inside of the multi-laminated substrate, the groove penetrates through the top layer substrate and extends into the bottom layer substrate, the active layer is arranged on the top layer substrate, and the first colloid covers the wall surface of the multi-laminated substrate, which is used for enclosing the groove. When the semiconductor device packaging structure is manufactured, the colloid arranged on the cutting surface of the multi-laminated substrate wafer can be utilized to protect the multi-laminated substrate wafer, and the risks that the layers of the multi-laminated substrate wafer crack and the cutting surface has microcracks are reduced.