TEST PATTERN GENERATING METHOD AND DEVICE
개요
발명자
Soyeon KANG; Kwangil So
IPC 분류
CPC 분류
A test pattern generating method includes obtaining design data with respect to a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting a transition delay (TD) fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation; and generating a second test pattern for detecting SA faults based on the design data and the PDFL.
원문 (중국어)
A test pattern generating method includes obtaining design data with respect to a circuit under test (CUT); generating, based on the design data, a first test pattern for detecting a transition delay (TD) fault and a pre-detected fault list (PDFL), wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation; and generating a second test pattern for detecting SA faults based on the design data and the PDFL.