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기록

Floating Point to Fixed Point Conversion

발명심사 중
2조회수
20청구항 · 3 독립항
§ Ⅰ

개요

IPC 분류

G6F 5/1G6F 7/48H3M 7/24

CPC 분류

G6F5/12G6F7/4824H3M7/24

A binary logic circuit for converting a number in floating point format into a fixed point format. An inverting hardware circuit inverts bit values of an exponent. A shifter coupled to the inverting hardware circuit receives a significand input comprising a contiguous set of the most significant bits of the significand and right-shifts the significand input by a number of bits equal to the value represented by p least significant bits of the inverted exponent to generate a shifter output, wherein p is dependent on an integer width iw or a fractional width fw. A multiplexer coupled to the shifter receives an input comprising a contiguous set of bits of the shifter output, and outputs the input if the most significant bit of the exponent is equal to zero.

원문 (중국어)

A binary logic circuit for converting a number in floating point format into a fixed point format. An inverting hardware circuit inverts bit values of an exponent. A shifter coupled to the inverting hardware circuit receives a significand input comprising a contiguous set of the most significant bits of the significand and right-shifts the significand input by a number of bits equal to the value represented by p least significant bits of the inverted exponent to generate a shifter output, wherein p is dependent on an integer width iw or a fractional width fw. A multiplexer coupled to the shifter receives an input comprising a contiguous set of bits of the shifter output, and outputs the input if the most significant bit of the exponent is equal to zero.