MANAGEMENT CIRCUIT FOR HIGH-BANDWIDTH MEMORY WITH MULTIPLE PROCESSING ELEMENTS
개요
발명자
Tong ZHANG; Jianping ZENG; Da ZHANG; Rekha PITCHUMANI; Yang Seok KI
IPC 분류
CPC 분류
A management technique for high bandwidth memory is disclosed. A processing management circuit (PMC) has a main executing circuit and a main memory and is configured to manage at least one processor operation performed by at least one of a first processing element (PE) or a second PE. A shared memory is configured to be shared by the PMC, the first PE, and the second PE. A memory management circuit (MMC) is configured to manage a memory operation on the shared memory based on a memory access by at least one of the PMC, the first PE, or the second PE. The at least one processor operation includes at least one of a program launch, a program execution, and an interrupt delivery.
원문 (중국어)
A management technique for high bandwidth memory is disclosed. A processing management circuit (PMC) has a main executing circuit and a main memory and is configured to manage at least one processor operation performed by at least one of a first processing element (PE) or a second PE. A shared memory is configured to be shared by the PMC, the first PE, and the second PE. A memory management circuit (MMC) is configured to manage a memory operation on the shared memory based on a memory access by at least one of the PMC, the first PE, or the second PE. The at least one processor operation includes at least one of a program launch, a program execution, and an interrupt delivery.