DETERMINISTIC MULTICORE SOFTWARE ARCHITECTURE
개요
발명자
Christopher J. Ambrose; Christopher D. Day; Simon E. Roper
IPC 분류
CPC 분류
A system for multi-core deterministic processing includes a processor and a memory including instructions which, when executed by the processor, cause the system at least to perform synchronizing a first processor core and a second processor core in time for access to a first shared memory and a second shared memory; causing, by the system, accessing by the first processor core of the first shared memory in a first time frame; causing, by the system, accessing by the second processor core of the second shared memory in the first time frame; causing, by the system, accessing by the first processor core of the second shared memory in a second time frame; and causing, by the system, accessing by the second processor core of the first shared memory in the second time frame.
원문 (중국어)
A system for multi-core deterministic processing includes a processor and a memory including instructions which, when executed by the processor, cause the system at least to perform synchronizing a first processor core and a second processor core in time for access to a first shared memory and a second shared memory; causing, by the system, accessing by the first processor core of the first shared memory in a first time frame; causing, by the system, accessing by the second processor core of the second shared memory in the first time frame; causing, by the system, accessing by the first processor core of the second shared memory in a second time frame; and causing, by the system, accessing by the second processor core of the first shared memory in the second time frame.