DEBUG CIRCUIT TO FREEZE SYSTEM DATAPATHS

原文（中国語）

Embodiments herein describe a system configured to transmit a freeze signal to all of a plurality of logic blocks within the system when an error or trigger event is detected in a logic block and allow each logic block to determine how to respond to the freeze signal, generate a freeze clock signal provided to a main functional logic of the logic block while permitting status and memory content to be read when the logic block enters into a clock freeze mode, generate a status freeze signal to stop a trace logic block from tracing incoming data, and collect a debug status of each of the plurality of logic blocks at a time the error or trigger event was detected or collect statistics within a same time sampling window across the system to perform a debug operation.