Z-Dimension Cache Layer Pipelining
개요
발명자
Paul James Moyer
IPC 분류
CPC 분류
Z-dimension cache layer pipelining is described. In one or more implementations, a device includes a stacked cache having a plurality of cache layers communicatively pipelined by an interconnect that outputs responses from the cache layers for processing during a common clock cycle. In one or more implementations, a system includes a stacked cache having a plurality of cache layers, with each cache layer implemented on a different respective die within a stack of dies, a cache controller configured to send requests to the cache layers and process responses received from the cache layers, and an interconnect configured to synchronize communication between the cache controller and the stacked cache by pipelining the responses to arrive at the cache controller during a common clock cycle.
원문 (중국어)
Z-dimension cache layer pipelining is described. In one or more implementations, a device includes a stacked cache having a plurality of cache layers communicatively pipelined by an interconnect that outputs responses from the cache layers for processing during a common clock cycle. In one or more implementations, a system includes a stacked cache having a plurality of cache layers, with each cache layer implemented on a different respective die within a stack of dies, a cache controller configured to send requests to the cache layers and process responses received from the cache layers, and an interconnect configured to synchronize communication between the cache controller and the stacked cache by pipelining the responses to arrive at the cache controller during a common clock cycle.