Variable Access Latency with Storage Array Extensions on Stacked Dies
개요
출원인
Advanced Micro Devices, Inc.
발명자
Gabriel Hsiuwei Loh; Brian William Thompto; John J. Wuu; Christopher Spence Oliver; Justin Allan Coppin; John M. King; Anthony Joseph Blybell; Anthony Jarvis
IPC 분류
CPC 분류
Variable access latency with storage array extensions on stacked dies. In one or more implementations, a system includes a storage array having a plurality of storage circuits implemented on different dies in a stack of dies, and control logic operable to receive responses from the storage circuits in reply to storage circuit requests forwarded through the stack of dies and output the responses according to a respective latency that delays each response based on a characteristic of a corresponding storage circuit that provides the response. In at least one implementation, a device includes a control logic that outputs responses from a stacked storage array having a plurality of storage circuits according to a respective latency that delays each response based on a characteristic of a corresponding storage circuit that provides the response.
원문 (중국어)
Variable access latency with storage array extensions on stacked dies. In one or more implementations, a system includes a storage array having a plurality of storage circuits implemented on different dies in a stack of dies, and control logic operable to receive responses from the storage circuits in reply to storage circuit requests forwarded through the stack of dies and output the responses according to a respective latency that delays each response based on a characteristic of a corresponding storage circuit that provides the response. In at least one implementation, a device includes a control logic that outputs responses from a stacked storage array having a plurality of storage circuits according to a respective latency that delays each response based on a characteristic of a corresponding storage circuit that provides the response.