REDUNDANT FUSED MULTIPLY-ACCUMULATE CIRCUITS FOR ERROR DETECTION IN MATRIX OPERATIONS UNIT

原文（中文）

A processor of an aspect includes a matrix operations unit. The matrix operations unit is to perform a matrix operation on a first source matrix and a second source matrix to generate a result matrix. The matrix operations unit includes a plurality of sets of circuits. The processor also includes a redundant set of circuits and a comparison unit coupled with the matrix operations unit and coupled with the redundant set of circuits. The comparison unit is to compare a first result generated by an indicated set of circuits of the plurality of sets of circuits with a second result generated by the redundant set of circuits. Each of the first and second results are to be generated based on a same set of input data from the first and second source matrices. Other processors, methods, and systems are disclosed.