Time-Optimal Placement Path Optimization Method for Surface Mounters

원문 (중국어)

The time-optimal placement path optimization method for surface mounters in this invention addresses the issue of excessively long total mounting time and low production efficiency in array-type layout circuit board assembly. This invention divides the placement points on the circuit board into grid rows based on component types and Y-axis coordinates, categorizes the placement points into different grid rows, and performs a global balance search. After identifying the placement points within each grid row that can be mounted simultaneously, it integrates two methods for the initial head-to-point assignment where the “simultaneous placement maximization” method promotes “approximate simultaneous placement” to the greatest extent, and the “progressive search rule” method avoids a purely local greedy search. A general solution framework for placement path optimization is constructed, where based on the initial assignment results, the unassigned remaining placement points are matched using the nearest insertion method, refining and deriving the final optimization result.