MERGED MEMORY DIES FOR WAFER-LEVEL TESTING
案件概要
発明者
Michele Piccardi; Kitae Park
IPC分類
CPC分類
A semiconductor wafer includes a plurality of memory dies disposed thereon. The plurality of memory dies are arranged as a plurality of superdies for testing, wherein each of the plurality of superdies comprises two or more of the plurality of memory dies. At least a subset of components of the two or more of the plurality of memory dies in each of the plurality of superdies are electrically shorted together to receive shared test signals from test equipment during the testing.
原文（中国語）
A semiconductor wafer includes a plurality of memory dies disposed thereon. The plurality of memory dies are arranged as a plurality of superdies for testing, wherein each of the plurality of superdies comprises two or more of the plurality of memory dies. At least a subset of components of the two or more of the plurality of memory dies in each of the plurality of superdies are electrically shorted together to receive shared test signals from test equipment during the testing.
外部リソース