CHAMBER ARRANGEMENTS WITH OFFSET UPPER REFLECTORS, SEMICONDUCTOR PROCESSING SYSTEMS, AND RELATED METHODS OF MAKING CHAMBER ARRANGEMENTS AND DEPOSITING MATERIAL LAYERS ONTO SUBSTRATES
卷宗概要
发明人
Robinson James; Nayna Khosla; Nitin Choudhary; Mitisha Surana; Yanfu Lu; Bubesh Babu Jotheeswaran; Amir Kajbafvala; Caleb Miskin; Alexandros Demos; Gregory Deye; Fan Gao; Jingxuan Lyu; Han Ye; Wentao Wang; Ion Hong Chao; Junwei Su
IPC 分类
CPC 分类
A chamber arrangement includes a chamber body having a chamber body with an injection end and a longitudinally opposite exhaust end, a substrate support arranged within the chamber body and supported for rotation therein rotation about a rotation axis, and an upper reflector supported above the chamber body and defining therein a laterally-outer first arcuate recess and a laterally-outer second arcuate recess. The laterally-outer first arcuate recess is separated from the rotation axis by a first arcuate recess lateral offset, the laterally outer second arcuate recess separated from the rotation axis by a second arcuate recess lateral offset, and the second arcuate recess lateral offset greater than or less than the first arcuate recess lateral offset. Semiconductor processing systems and material layer deposition methods are also described.
原文（中文）
A chamber arrangement includes a chamber body having a chamber body with an injection end and a longitudinally opposite exhaust end, a substrate support arranged within the chamber body and supported for rotation therein rotation about a rotation axis, and an upper reflector supported above the chamber body and defining therein a laterally-outer first arcuate recess and a laterally-outer second arcuate recess. The laterally-outer first arcuate recess is separated from the rotation axis by a first arcuate recess lateral offset, the laterally outer second arcuate recess separated from the rotation axis by a second arcuate recess lateral offset, and the second arcuate recess lateral offset greater than or less than the first arcuate recess lateral offset. Semiconductor processing systems and material layer deposition methods are also described.