MEMORY-COMPUTING INTEGRATED CHIP ARCHITECTURE, PACKAGING METHOD AND APPARATUS

원문 (중국어)

The present disclosure relates to the technical field of memory-computing integrated chips, and in particular, to a memory-computing integrated chip architecture, a packaging method and an apparatus for a memory-computing integrated chip. The memory-computing integrated chip architecture includes: a plurality of first chips, each integrated with one or more arrays of memory-computing integrated cells, wherein the one or more arrays of memory-computing integrated cells are used for computing with received data; and one or more second chips, each integrated with one or more peripheral circuit IP cores, wherein the one or more arrays of memory-computing integrated cells are coupled to the one or more peripheral circuit IP cores via one or more 10 communication paths, and wherein the one or more communication paths are arranged based on one or more of an operation property and an arrangement of the one or more arrays of memory-computing integrated cells of the plurality of first chips.