DIGITAL DUTY CYCLE CORRECTOR CIRCUIT
개요
출원인
Taiwan Semiconductor Manufacturing Company, Ltd.
발명자
Chang-Yi Li
IPC 분류
CPC 분류
A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.
원문 (중국어)
A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.