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富士广半导体（深圳）有限公司

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№ CN122988048AInvention
Unknown

内嵌SNN硬件加速器的异构微控制器架构及方法

本发明公开了一种内嵌SNN硬件加速器的异构微控制器架构及数据处理方法，涉及微控制器与神经形态计算交叉技术领域。所述异构微控制器架构包括：通用RISC‑V处理器核，用于执行系统控制逻辑与非神经网络计算任务；SNN硬件加速器，内部包含可配置的神经元计算阵列，用于执行脉冲神经网络的膜电位更新及脉冲发放判定；外设接口模块，用于连接外部事件传感器，接收原始异步脉冲信号；事件路由器，其输入端连接所述外设接口模块，其输出端连接所述SNN硬件加速器；紧耦合共享数据缓存，分别连接所述通用RISC‑V处理器核与所述SNN硬件加速器。本发明解决了现有技术存在的SNN推理能效比低、响应延迟高以及CPU负担重的问题。

❖富士广半导体（深圳）有限公司卢仕广; 卢奇裕; 卢晓薇; 庄雪滢Oct 27, 2026§ 2/10 ClaimsG06N 3/063 (2023.01), G06N 3/049 (2023.01), G06N 5/04 (2023.01) +1