可容忍中间回路故障的级联多回路锁相环(PLL)时钟同步器
本申请为一种级联多回路锁相环(CMPLL),包括根据层级排列的一主回路及多个次级回路。所述主回路在层级中最高,且每个次级回路由层级中更高回路的组件完成。较低层级的每个回路提供相应的校正信号,用以校正一或多个较高层级回路的规范频率的任何漂移。所述CMPLL还包括一组旁路电路,每个旁路电路耦合在第一回路与在层级中至少高出一级的第二回路之间,并在越级层回路不工作时,将所述第一回路的替代信号作为对应校正信号传递至所述第二回路。
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