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芯片收发器延迟测试方法、装置、终端设备及存储介质
InventionUnknown
10Claims · 4 independent
§ Ⅰ
Dossier Overview
Inventor
刘育才
Filing Date
Apr 10, 2025
Publication Date
Oct 20, 2026
IPC Classification
H04B 17/10 (2015.01)H04B 17/15 (2015.01)H04B 17/00 (2015.01)H04B 17/20 (2015.01)H04B 17/29 (2015.01)
本发明公开了一种芯片收发器延迟测试方法、装置、终端设备及存储介质,属于通信技术领域,其中方法包括:向目标芯片收发器发送测试数据,在所述目标芯片收发器接收到数据控制信号脉冲时,将测试数据更改为标记数据,并触发开始脉冲;确定测试数据跳变为标记数据的时间为跳变时间,根据跳变时间和开始脉冲触发时间确定目标芯片收发器的发送延迟,本发明能够解决现有技术中直接在FPGA芯片内部使用并行位宽的计数器做延迟统计,存在并行时钟周期的跨时钟域不确定性误差,导致收发器延迟测试的准确性较低的技术问题。
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