MEMORY CONTROLLER AND OPERATION METHOD THEREOF
Dossier Overview
Applicant
SK hynix Inc.; Seoul National University R&DB Foundation
Inventor
Sungjun Jung; Sangwoo Kwon; Jaewook Lee; Yongsang Park; Young Ook Song
IPC Classification
CPC Classification
A memory controller includes a host interface circuit configured to receive a host read request, a host write request, and a data block corresponding to the host write request from a host; a compression control circuit configured to generate a compressed data block by compressing the data block based on an N:M sparsity rule and generate a metadata block including metadata for data elements included in the compressed data block; a scheduler configured to schedule a first write command for writing the compressed data block and a second write command for writing the metadata block; and a memory interface circuit configured to transmit a memory command output from the scheduler to a memory device, wherein N and M are natural numbers and an M is greater than N.
Original (Chinese)
A memory controller includes a host interface circuit configured to receive a host read request, a host write request, and a data block corresponding to the host write request from a host; a compression control circuit configured to generate a compressed data block by compressing the data block based on an N:M sparsity rule and generate a metadata block including metadata for data elements included in the compressed data block; a scheduler configured to schedule a first write command for writing the compressed data block and a second write command for writing the metadata block; and a memory interface circuit configured to transmit a memory command output from the scheduler to a memory device, wherein N and M are natural numbers and an M is greater than N.
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