MEMORY LATENCY AWARE TILING FOR GENERALIZED MATRIX MULTIPLICATIONS ON PARALLEL PROCESSORS

원문 (중국어)

A processor includes a plurality of processing elements. Each processing element is configured to obtain a first plurality of submatrices from a first input matrix and a second plurality of submatrices from a second input matrix. The first and second plurality of submatrices, for at least a first iteration of a plurality of matrix multiply iterations, each include at least one submatrix that is distinct from submatrices obtained by the other processing elements. The processing element performs one or more matrix multiplication operations on the first plurality of submatrices and the second plurality of submatrices to generate partial results for an output submatrix of an output matrix associated with the processing element. The processing element generates a portion of the output matrix by combining the partial results in the memory for the output submatrix. The output submatrices generated by each of the processing elements form the output matrix.