SELECTIVE TRACING BASED ON ISOLATION IN SOFTWARE BASED DEVICES
Dossier Overview
Applicant
NXP USA, Inc.
Inventor
Ayushi Agarwal; Aditya Vikram Chopra; Juhee Mala
IPC Classification
CPC Classification
An apparatus and method are disclosed for a System on Chip (SoC) which includes a central interconnect fabric connected between a plurality of initiators and targets, where the central interconnect includes one or more debug trace probes for connection to a debugger, where each debug trace probe is connected with debug firewall control logic configured to allow a data trace packet from a first cohort to be traced out to the debug trace probe only if the data trace packet includes a CID value associated with the first cohort that matches a CCID value associated with a configuring cohort which configures the debug trace probe, and where the debug firewall control logic includes a secure trace enable multiplexer connected to packet capture control logic which is configured to output a packet capture enable signal indicating whether the data trace packet is a secure packet or unsecure packet.
Original (Chinese)
An apparatus and method are disclosed for a System on Chip (SoC) which includes a central interconnect fabric connected between a plurality of initiators and targets, where the central interconnect includes one or more debug trace probes for connection to a debugger, where each debug trace probe is connected with debug firewall control logic configured to allow a data trace packet from a first cohort to be traced out to the debug trace probe only if the data trace packet includes a CID value associated with the first cohort that matches a CCID value associated with a configuring cohort which configures the debug trace probe, and where the debug firewall control logic includes a secure trace enable multiplexer connected to packet capture control logic which is configured to output a packet capture enable signal indicating whether the data trace packet is a secure packet or unsecure packet.
External Resources