APPARATUS INCLUDING MEMORY MAT EDGE STRUCTURE

Original (Chinese)

Some embodiments of the disclosure provide an apparatus comprising a memory mat including a memory cell portion, a dummy portion adjacent to the memory cell portion, and an edge portion adjacent to the dummy portion. The memory cell portion includes a first capacitor structure, a first redistribution layer structure coupled to the first capacitor structure, and a cell contact structure coupled to the redistribution layer structure, and the first capacitor structure is coupled to the cell contact structure by the first redistribution layer structure. The dummy portion includes a second capacitor structure and a second redistribution layer structure coupled to the second capacitor structure. The edge portion includes an outermost capacitor structure and a conductive layer structure coupled to the outermost capacitor structure, and the conductive layer structure is at a position higher than the first and second redistribution layer structures on the semiconductor substrate.