MEMORY WITH REDUNDANT READ OPTIMIZATION
Dossier Overview
Applicant
QUALCOMM Incorporated
Inventor
Asheesh Singh BAGHEL; Amit DUGGAL; Sateeshkumar INJARAPU
IPC Classification
CPC Classification
A memory is provided with a redundant read logic circuit that detects whether a current read operation should proceed as a redundant or non-redundant read operation. In a redundant read operation, the memory does not assert a word line voltage nor does it enable any sense amplifiers. The data for a redundant read operation is thus not provided by the memory but instead is retrieved from a global input/output (GIO) memory circuit such as a GIO latch.
Original (Chinese)
A memory is provided with a redundant read logic circuit that detects whether a current read operation should proceed as a redundant or non-redundant read operation. In a redundant read operation, the memory does not assert a word line voltage nor does it enable any sense amplifiers. The data for a redundant read operation is thus not provided by the memory but instead is retrieved from a global input/output (GIO) memory circuit such as a GIO latch.
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