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APPARATUS AND METHODS FOR REFERENCE READ TECHNIQUES FOR THRESHOLD SELECTOR DEVICE MEMORY

发明专利审中
20权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Christopher J. Petti; Raj Ramanujan; Dimitri Houssameddine; Mark Lin

IPC 分类

G11C 13/

CPC 分类

G11C13/4G11C13/28G11C13/3G11C13/69G11C2013/52G11C2213/30G11C2213/76

An apparatus includes memory array having a first memory cell including a first two-terminal element having first and second threshold voltages, a second memory cell including a second two-terminal element having third and fourth threshold voltages, and a control circuit coupled to the memory array. The control circuit is configured to cause the first two-terminal element to have the first threshold voltage, and cause the second two-terminal element to have either the third threshold voltage or the fourth threshold voltage, apply a third voltage signal that increases at a first ramp rate to the first memory cell and the second memory cell, determine that the first memory cell switches from a non-conducting state to a conducting state, and read the second memory cell using the third voltage signal a first predetermined delay time after the first memory cell switches from the non-conducting state to the conducting state.

原文(中文)

An apparatus includes memory array having a first memory cell including a first two-terminal element having first and second threshold voltages, a second memory cell including a second two-terminal element having third and fourth threshold voltages, and a control circuit coupled to the memory array. The control circuit is configured to cause the first two-terminal element to have the first threshold voltage, and cause the second two-terminal element to have either the third threshold voltage or the fourth threshold voltage, apply a third voltage signal that increases at a first ramp rate to the first memory cell and the second memory cell, determine that the first memory cell switches from a non-conducting state to a conducting state, and read the second memory cell using the third voltage signal a first predetermined delay time after the first memory cell switches from the non-conducting state to the conducting state.