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MEMORY READ CALIBRATION BASED ON MEMORY DEVICE-ORIGINATED METRICS CHARACTERIZING VOLTAGE DISTRIBUTIONS

InventionPending
6views
20Claims · 3 independent
§ Ⅰ

Dossier Overview

Inventor

Dung Viet Nguyen; Patrick R. Khayat; Zhengang Chen; Shantilal Rayshi Doru; Hope Abigail Henry

IPC Classification

G11C 16/34G11C 16/26

CPC Classification

G11C16/3404G11C16/26

Described are systems and methods for memory read calibration based on memory device-originated metrics. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a first metric indicative of a first quantity of data stored in a subset of memory cells associated with at least one non-conducting bitline; determining a first read voltage adjustment value; performing a read operation with respect to the subset of memory cells based on the first read voltage adjustment value; receiving a second value of a second metric indicative of a second quantity of data stored in the subset of memory cells associated with at least one non-conducting bitline; determining a second read voltage adjustment value; and applying the second read voltage adjustment value for reading the plurality of memory cells.

Original (Chinese)

Described are systems and methods for memory read calibration based on memory device-originated metrics. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a first metric indicative of a first quantity of data stored in a subset of memory cells associated with at least one non-conducting bitline; determining a first read voltage adjustment value; performing a read operation with respect to the subset of memory cells based on the first read voltage adjustment value; receiving a second value of a second metric indicative of a second quantity of data stored in the subset of memory cells associated with at least one non-conducting bitline; determining a second read voltage adjustment value; and applying the second read voltage adjustment value for reading the plurality of memory cells.

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