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COMMUNICATION CIRCUITS INCLUDING A DIFFERENTIAL TO QUADRATURE PHASE GENERATOR

发明专利审中
20权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Wei Shuo LIN

IPC 分类

H4L 7/H3K 5/H3L 7/81H4L 7/33

CPC 分类

H4L7/25H3K5/H3L7/814H4L7/337H3K2005/52

A device includes a transmission clock circuit that includes a phase interpolator circuit and a transmission differential to quadrature phase generator. The phase interpolator circuit interpolates phases and provides phase interpolated first clock signals and phase interpolated second clock signals. The transmission differential to quadrature phase generator, duty cycle corrects each of the phase interpolated first clock signals and the phase interpolated second clock signals, quadrature error corrects each of the duty cycle corrected phase interpolated first clock signals and the duty cycle corrected phase interpolated second clock signals, outputs transmission clock signals based on the quadrature error corrected duty cycle corrected phase interpolated first clock signals, and outputs multiple clock phases and a track signal based on the quadrature error corrected duty cycle corrected phase interpolated second clock signals.

原文(中文)

A device includes a transmission clock circuit that includes a phase interpolator circuit and a transmission differential to quadrature phase generator. The phase interpolator circuit interpolates phases and provides phase interpolated first clock signals and phase interpolated second clock signals. The transmission differential to quadrature phase generator, duty cycle corrects each of the phase interpolated first clock signals and the phase interpolated second clock signals, quadrature error corrects each of the duty cycle corrected phase interpolated first clock signals and the duty cycle corrected phase interpolated second clock signals, outputs transmission clock signals based on the quadrature error corrected duty cycle corrected phase interpolated first clock signals, and outputs multiple clock phases and a track signal based on the quadrature error corrected duty cycle corrected phase interpolated second clock signals.