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案件記録

SEMICONDUCTOR STRUCTURE INCLUDING DEEP TRENCH CAPACITORS AND METHODS OF FABRICATION THEREOF

発明審査中
1閲覧数
20請求項 · 3 独立
§ Ⅰ

案件概要

発明者

Tzu Jung TIEN; Cheung CHENG; Chen-Hsuan YEN; Fu-Chiang KUO

IPC分類

H10D 1/H10D 1/68

CPC分類

H10D1/42H10D1/714H10D1/716

In an embodiment, a semiconductor structure includes a substrate having a plurality of deep trenches oriented in a first direction and a second direction and a plurality of mesas interposed by the deep trenches. The semiconductor structure also includes a plurality of capacitor groups, wherein each of the capacitor groups includes a stack of conductive layers and node dielectric layers alternately disposed in the deep trenches and a first conductive plug disposed on a first layer of the conductive layers. The semiconductor structure also includes an isolation wall penetrating through the stack of the conductive layers and the node dielectric layers and into at least one of the mesas, the isolation wall being a close loop in a top view.

原文(中国語)

In an embodiment, a semiconductor structure includes a substrate having a plurality of deep trenches oriented in a first direction and a second direction and a plurality of mesas interposed by the deep trenches. The semiconductor structure also includes a plurality of capacitor groups, wherein each of the capacitor groups includes a stack of conductive layers and node dielectric layers alternately disposed in the deep trenches and a first conductive plug disposed on a first layer of the conductive layers. The semiconductor structure also includes an isolation wall penetrating through the stack of the conductive layers and the node dielectric layers and into at least one of the mesas, the isolation wall being a close loop in a top view.

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