元の名称記録: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A semiconductor device includes a bit line pre-charger and a buffer circuit. The bit line pre-charger is configured to charge at least one bit line when a first control signal has a first voltage level. The buffer circuit is configured to generate the first control signal. During a first standby period, the buffer circuit adjusts the first control signal to a second voltage level different from the first voltage level.

A signal generation circuit includes a loopback path and a signal generator including an inverter including an output terminal coupled to a first end of the loopback path, a transistor coupled between a second end of the loopback path and a power distribution node, a buffer including an input terminal configured to receive a clock signal, a first logic gate including a first input terminal coupled to the buffer input terminal, a second input terminal coupled to an output terminal of the buffer, and an output terminal coupled to an input terminal of the inverter and a gate of the transistor, and a second logic gate including a first input terminal coupled to the buffer input terminal, a second input terminal coupled to the second end of the loopback path, and an output terminal configured to output an output signal.

A method includes retrieving a first front opening unified pod (FOUP) from a FOUP stocker utilizing an interface module equipped with a transfer module; transporting the retrieved first FOUP via the transfer module across a first path within the interface module to align the first FOUP with an available first load port of a process tool; loading the first FOUP on the first load port; delivering wafers from the first FOUP to the process tool via the first load port to initiate a wafer processing operation using the wafers.

A semiconductor device includes a circuit having a first pin; a first conductor extending in a first direction, the first circuit being between a second conductor and a first side of the first conductor; a circuit having a second pin; and a connection to couple a signal between the first pin and the second pin, the connection including: a first conductive element extending in a second direction, the first conductive element connected to the first pin on the first side of the first conductor; a first via structure connecting the first conductive element to a back of the substrate, including a first feed-through via (FTV) on a second side of the first conductor; a second via structure to provide the signal to a front of the substrate, the second via structure including a second FTV; and a second conductive element connected to the second via structure and the second pin.

In an embodiment, a semiconductor structure includes a substrate having a plurality of deep trenches oriented in a first direction and a second direction and a plurality of mesas interposed by the deep trenches. The semiconductor structure also includes a plurality of capacitor groups, wherein each of the capacitor groups includes a stack of conductive layers and node dielectric layers alternately disposed in the deep trenches and a first conductive plug disposed on a first layer of the conductive layers. The semiconductor structure also includes an isolation wall penetrating through the stack of the conductive layers and the node dielectric layers and into at least one of the mesas, the isolation wall being a close loop in a top view.

An integrated circuit includes a resistor circuit that includes a first metal resistor strip and a first and second metal line. The first metal resistor strip extends in a first direction, is on a first level, and is over a semiconductor substrate. The first metal line extends in a second direction, and is on a second level. The second metal line extends in the second direction, is on the second level, and is separated from the first metal line in the first direction. The first and second metal line are electrically connected to the first metal resistor strip. The first metal resistor strip is a first dummy gate. The first transistor includes a first metal gate strip extending in the first direction, being on the first level, and being separated from the first metal resistor strip in at least the first direction.

Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The structure includes a first semiconductor layer disposed over a substrate, a source/drain region disposed adjacent the first semiconductor layer, a gate spacer disposed over the first semiconductor layer, a native oxide layer disposed between the gate spacer and the source/drain region and between the gate spacer and the first semiconductor layer, a gate dielectric layer disposed between the native oxide layer and the first semiconductor layer, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode layer includes a first portion having a first width and a second portion having a second width greater than the first width.

Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.