Chip stacking structure and electronic equipment
Source: EPO OPS
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Dossier Overview
Application number
CN202310312057
Inventor
CHEN LONGJUN; HUANG TIANQIANG; LIU RONGBIN; WANG ZHENGBO; LIU YUN
Filing Date
Mar 21, 2023
Publication Date
Sep 24, 2024
Patent Family ID
92763362
IPC Classification
CPC Classification
The embodiment of the invention provides a chip stacking structure and electronic equipment, relates to the technical field of chip manufacturing, and aims to solve the problem that the plane size of a chip is relatively large. In the chip stacking structure, a third bare chip, a second bare chip and a first bare chip are sequentially stacked on a carrier plate. The first rewiring layer and the first interface element of the first bare chip form a first interface circuit, and the second rewiring layer and the second interface element of the second bare chip form a second interface circuit. The first conduction structure at least penetrates through the second bare chip and the third bare chip, and the second conduction structure at least penetrates through the third bare chip. The first interface circuit of the first bare chip and the second interface circuit of the second bare chip are electrically connected with other components through a first insulated conduction structure and a second insulated conduction structure respectively.
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