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SMT core controller, compiler and method for executing compiled runtime code on SMT core controller

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81648624Family
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Dossier Overview

Applicant

HUAWEI TECH CO LTD

Application number

CN20228092077

Inventor

PETUSHKOV IGOR VYACHESLAVOVICH; WANG KEBING; LAMPRET DAMJAN

Filing Date

Mar 17, 2022

Publication Date

Sep 27, 2024

Patent Family ID

81648624

IPC Classification

G06F8/41G06F9/38

CPC Classification

G06F8/45G06F9/3838G06F9/3851G06F9/3887G06F9/3888G06F9/467G06F8/427G06F8/452G06F8/454G06F8/456

The synchronous multi-thread core controller is configured to receive compiled runtime code including a plurality of threads and further execute at least two of the plurality of threads in parallel using the memory. Further, the SMT core controller determines whether there is any storage collision between the at least two threads executing in parallel. And the SMT core controller cancels the fiber thread with any storage conflict, re-executes the fiber thread with the storage conflict, and submits any storage operation of the fiber thread without the storage conflict to the SMT core memory. Executing at least two of the plurality of threads in parallel can improve superscalar pipeline utilization and parallelism of a single thread. In addition, the SMT core controller may increase the overall throughput of multi-threaded execution while improving efficiency and improving single-threaded execution.

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