原始名称记载: Advanced Micro Devices, Inc.

In accordance with the described techniques, a device includes a host processor, a memory, and a memory physical layer. The memory physical layer enters an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer while the memory is inactive with respect to servicing memory requests of the host processor. In addition, the memory physical layer exits the enhanced low power state responsive to the memory being active with respect to servicing memory requests of the host processor and/or at least one memory request being enqueued for servicing by the memory.

In aspects of near-memory random and pattern-based data generation, a system includes a number generator circuit configured to generate a sequence of numbers, a memory chip configured to store the sequence of numbers, and a memory interface configured to enable communication between the number generator circuit and the memory chip. In one or more implementations, the number generator circuit includes a random number generator circuit configured to generate the sequence of numbers as a sequence of random numbers. Additionally, or alternatively, the number generator circuit includes a pattern fill function configured to generate the sequence of numbers based on a pattern. In other aspects of near-memory random and pattern-based data generation, a memory device includes a base layer, a memory interface, and a number generator circuit interleaved among the base layer and the memory interface.

Instruction deltas for processing-in-memory divergence are described. In one or more implementations, a system includes a memory and a processing-in-memory component configured to identify an instruction delta based on one or more undefined portions of an instruction of a PIM command and decode the instruction delta into one or more defined portions of the instruction to be used in place of the undefined portions to execute the instruction. In one or more implementations, a processing-in-memory component includes at least one computational unit of an in-memory processor that identifies an instruction delta based on one or more undefined portions of an instruction of a PIM command, decodes the instruction delta into one or more defined portions of the instruction to be used during execution in place of the undefined portions, and executes the instruction based on the defined portions.

The disclosed processing device can fuse two instructions into a fused instruction and save metadata corresponding to one of the instructions. The metadata allows the instruction to be performed as needed to generate intermediate values not output from the fused instruction. Various other methods, systems, and computer-readable media are also disclosed.

In accordance with the described techniques, a system includes a host processor and a control processor communicatively coupled to an acceleration processor. The control processor includes a management thread. The management thread receives requests to execute multiple workloads of multiple applications on the acceleration processor. Further, the management thread creates task threads on the control processor allocated to corresponding applications and corresponding partitions of the acceleration processor. The task threads receive the multiple workloads from the host processor, and dispatch the multiple workloads to corresponding partitions to be executed by the acceleration processor in parallel.

With some techniques described herein, efficiency of data processing operations may be increased by avoiding loading of data and/or avoiding execution of instructions that would operate on sparse data. In some implementations described herein, using metadata or other indications of whether data meets at least one criterion (e.g., a sparsity criterion), instructions may be executed on sparse data without incurring the time cost of loading the sparse data from a storage (e.g., memory), such as by creating new sparse data in a way that may be faster than loading it from memory or by performing the instructions with a representation of the sparse data or an indication of what an output of processing the sparse data would have been. In some implementations, additionally or alternatively some instructions may not be executed or may not be scheduled for execution, if the instructions are to process sparse data.

A central processing unit (CPU) is disclosed. The CPU includes: a physical register file (PRF) including a plurality of physical registers; an instruction queue configured to store an instruction identifying an opcode, a source operand register, and a destination operand register; and an allocator, configured to allocate a first physical register to the destination operand register, where the first physical register has a first changeable bit size corresponding with a result bit size of the destination operand register.

The disclosed device includes a processor core and a management core. The management core can intercept error interrupts indicating errors for the processor core. The management core can process the error while the processor core continues operations, and can also cloak the error from an operating system. Various other methods, systems, and computer-readable media are also disclosed.

Embodiments herein describe including one or more error indicating bits in a task pointer (e.g., a WQE) to tell a downstream queue or stage, such as a pipeline, that an upstream queue or stage detected a DMA error. The communication from each upstream stage or pipeline to the next is typically through posting WQEs into the next stage queue and ringing doorbells. The embodiments herein use one or more error indicator bits (e.g., color bits) in the WQE to inform a downstream queue (e.g., a downstream pipeline) that the upstream queue/pipeline detected a failed DMA operation. The downstream queue can then perform error handling where it reclaims the resources allocated for the WQE (such as an intermediate buffer).

The disclosed device includes a processor core and a management core. The management core can intercept error interrupts indicating errors for the processor core. The management core can process the error while the processor core continues operations, and can also cloak the error from an operating system. The management core can also provide the errors to a baseboard controller for storing in a non-volatile memory. Various other methods, systems, and computer-readable media are also disclosed.

Embodiments herein describe a system configured to transmit a freeze signal to all of a plurality of logic blocks within the system when an error or trigger event is detected in a logic block and allow each logic block to determine how to respond to the freeze signal, generate a freeze clock signal provided to a main functional logic of the logic block while permitting status and memory content to be read when the logic block enters into a clock freeze mode, generate a status freeze signal to stop a trace logic block from tracing incoming data, and collect a debug status of each of the plurality of logic blocks at a time the error or trigger event was detected or collect statistics within a same time sampling window across the system to perform a debug operation.

An asymmetrical last level cache is described. In one or more implementations, a system includes a first set of cores with an associated first last level cache and a second set of cores with an associated second last level cache. The first and second last level caches are asymmetrical, meaning they have differing characteristics such as size, speed, replacement policy, or associativity. This configuration allows for dynamic allocation of tasks to the cores based on a combination of the performance characteristics of the cores and the attributes of their associated last level caches.

Systems and techniques for software-guided prefetch throttling based on memory region boundaries are described. In one example, a processor includes a cache system having a cache system and a hardware prefetcher associated with a cache level of the cache system. The hardware prefetcher receives a boundary hint from a workload of an execution unit that accesses the cache level. The hardware prefetcher throttles prefetch requests based on the memory hint being satisfied. The described techniques overcome cache pollution from conventional prefetchers without limiting a prefetcher's ability to identify and respond to stride access patterns.

In accordance with described techniques for balanced latency stacked cache, a stacked cache system includes a first cache die and at least a second cache die in a stacked orientation with the first cache die. The stacked cache system includes cache control circuitry that is centrally located in the stacked cache system. The stacked cache system also includes connection vias configured vertically in a center of the stacked cache system as interconnected inputs and outputs of the first cache die and the second cache die.

An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.

Z-dimension cache layer pipelining is described. In one or more implementations, a device includes a stacked cache having a plurality of cache layers communicatively pipelined by an interconnect that outputs responses from the cache layers for processing during a common clock cycle. In one or more implementations, a system includes a stacked cache having a plurality of cache layers, with each cache layer implemented on a different respective die within a stack of dies, a cache controller configured to send requests to the cache layers and process responses received from the cache layers, and an interconnect configured to synchronize communication between the cache controller and the stacked cache by pipelining the responses to arrive at the cache controller during a common clock cycle.

Variable access latency with storage array extensions on stacked dies. In one or more implementations, a system includes a storage array having a plurality of storage circuits implemented on different dies in a stack of dies, and control logic operable to receive responses from the storage circuits in reply to storage circuit requests forwarded through the stack of dies and output the responses according to a respective latency that delays each response based on a characteristic of a corresponding storage circuit that provides the response. In at least one implementation, a device includes a control logic that outputs responses from a stacked storage array having a plurality of storage circuits according to a respective latency that delays each response based on a characteristic of a corresponding storage circuit that provides the response.

A device includes a plurality of chiplets. At least one pair of chiplets of the plurality of chiplets is coupled to one another. Each chiplet of the plurality of chiplets includes a Root-of-Trust (RoT) circuit and a trust level mapping circuit. For each chiplet of the plurality of chiplets, the trust level mapping circuit of the chiplet is configured to modify trust levels of transactions received from a different chiplet of the plurality of chiplets.

A geometry compression format is described. The compression format eliminates the need to store duplicate vertex information by storing unique vertices in each compressed data structure. Different triangles can refer to the same vertex using an index value, which means that even if the same vertex is used multiple times in the compressed data structure, the entirety of the vertex information (e.g., positional information) does not need to be stored multiple times. While the format provides good compression characteristics, improvement can be gained by eliminating the indices and instead using an indication of an “implicit geometry.” The implicit geometry is a commonly-used geometry type that indicates a particular correspondence between unique vertices and triangles. In other words, by indicating an implicit geometry type, it is automatically known which vertices make up which triangles, and explicit index information does not need to be stored in the compressed data structure.

A geometry compression format is described. The compression format eliminates the need to store duplicate vertex information by storing unique vertices in each compressed data structure. Different triangles can refer to the same vertex using an index value, meaning that even if the same vertex is used multiple times in the compressed data structure, the entirety of the vertex information (e.g., positional information) does not need to be stored multiple times. An improvement includes representing further subdivision of the geometry in an efficient manner to represent highly detailed geometry. The subdivision can be specified by sideband information which can specify any of a variety of types of information.