Original name record: SK hynix Inc.

A device for selectively removing a perfluorinated compound includes an adsorption electrooxidation tank, including a reaction unit having a plurality of electrodes and granular activated carbon, configured to oxidize and decompose a perfluorinated compound in raw water through adsorption and electrooxidation; a power supply device configured to supply power to the adsorption electrooxidation tank; and a head adjustment pipe unit configured to maintain a water level within the reaction unit at a height greater than or equal to a reaction height of the electrodes.

A semiconductor device includes a receiving circuit, an oscillator code generation circuit, and a control circuit. The receiving circuit receives a clock signal and data, delays the clock signal by a clock delay time to generate an internal clock signal, and captures the data with the internal clock signal. The oscillator code generation circuit generates an oscillation signal having a period of N times the clock delay time, wherein N is a positive integer, and generates an oscillator code based on the oscillation signal. The control circuit controls the oscillator code generation circuit in response to at least one external signal. The at least one external signal including a chip enable signal.

Information on a free storage region may be managed by using a free storage region where compressed data is not stored among the physical storage regions storing compressed data in memory, and the movement of information on the free storage region may be managed by adding a free buffer in addition to a service queue for processing allocation and return of the physical storage region. Accordingly, it is possible to reduce the delays due to accessing a memory when allocating or returning a physical storage region, thereby improving the memory operation performance.

A memory device may include: a plurality of memory cells; a data manager for receiving data from the plurality of memory cells, and generating sub-data groups having a predetermined size, based on the received data; and a data compressor for detecting first-value bits having a first logic value among the bits in the received data, determining a number of target bits corresponding to each of the sub-data groups among the first-value bits to become 1 or less per sub-data group, and generating a plurality of compressed-data chunks including a logic value of the target bits and position information representing a position of the target bits in the data.

A memory system includes a controller configured to transmit a reset write command and reset write data, and transmit a set write command and set write data; and at least one memory device configured to generate seed data by performing a first operation on the reset write data and read data read out from a target memory area in response to the reset write command, generate write data by performing a second operation on the seed data and the set write data in response to the set write command, and write back the write data to the target memory area.

A computational storage system may include a computing circuit configured to execute an operation requested by a host, a storage device for storing data, and a switch configured to establish a connection among the host, the computing circuit and the storage device based on a topology for the host, the computing circuit and the storage device. The switch may establish the connections so that the host can directly access the computing circuit and the storage device when the topology is a first topology, and may establish the connections so that the host can directly access the computing circuit but the host cannot directly access the storage device when the topology is a second topology.

Provided herein may be a data storage device and a method of operating the same. A data storage device for dynamically managing a map update cycle may include a memory device configured to store data, and a controller configured to adjust a cycle at which map data corresponding to write requests received from a host for a preset reference time is stored in the memory device, depending on a number of small data chunk write requests that are write requests for data having a preset unit size, among the write requests.

A memory system may include: a nonvolatile memory device; and a controller suitable for generating first map information which maps physical addresses of the nonvolatile memory device to logical addresses received from a host, selecting some segments of the first map information as second map information, and outputting the second map information to the host, the controller may determine whether the second map information is updated, and may determine updated map segments as third map information, and the controller may output information to the host indicating the third map information corresponding to a command received from the host.

According to an embodiment of the present technology, a storage device may include a memory device including a secure storage area for storing therein data to be accessed according to authentication; an access mode memory configured to store therein information of device access mode regarding an operation mode for the secure storage area; and a memory controller configured to receive a command regarding the secure storage area from an external host and process the command according to whether information of host access mode included in the command matches the information of the device access mode.

A memory device includes a first driving circuit configured to supply a second voltage to a supply terminal of a first voltage when the first voltage is lower than a first threshold voltage, in response to a first enable signal; a second driving circuit configured to supply the second voltage to the supply terminal of the first voltage when the first voltage is lower than a second threshold voltage, in response to a second enable signal, the second threshold voltage having a lower voltage level than the first threshold voltage; and a sense amplification circuit coupled to the supply terminal of the first voltage.

A semiconductor device includes a clock receiver configured to buffer a data clock signal and an inverted data clock signal to generate a buffer clock signal and an inverted buffer clock signal, respectively, and configured to generate a division clock signal based on the buffer clock signal and the inverted buffer clock signal, and a data receiver configured to buffer data based on the division clock signal to generate internal data.

A semiconductor device includes a receiving circuit, an oscillator code generation circuit, and a control circuit. The receiving circuit receives a clock signal and a data signal including data, delays the clock signal by a clock delay time to generate an internal clock signal, and captures the data using the internal clock signal. The oscillator code generation circuit generates an oscillation signal having a period of N times the clock delay time, wherein N is a positive integer, and generates an oscillator code based on the oscillation signal. The control circuit controls the oscillator code generation circuit in response to at least one external signal, during an initialization stage after power-on.

A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.

An auxiliary power supply includes an auxiliary power storage configured to store power that is input to the auxiliary power supply and a control circuit, wherein the control circuit is configured to charge, for a reference time amount after the power is input to the auxiliary power supply, the auxiliary power storage by a first current source having a preset peak current level, determine, after the reference time amount, that the auxiliary power supply is in a slow charging state when a voltage level that is charged to the auxiliary power storage by the first current source for the reference time amount is lower than a reference voltage level, and increase, in response to the slow charging state, the peak current level to charge the auxiliary power storage by a second current source having the increased peak current level that is greater than the preset peak current level.

A storage device includes a group of non-volatile memory cells, page buffers coupled to the non-volatile memory cells and a control circuit. The control circuit performs one or more program loops on the group according to program data loaded on the page buffers, each of the program loops include a series of consecutive program pulse application operations and a series of consecutive verification operations.

A semiconductor device includes transistors disposed on a substrate; and interconnection layers disposed over the transistors. The interconnection layers include a lower interconnection layer and an upper interconnection layer disposed over the lower interconnection layer. The upper interconnection layer includes first patterns extending in parallel in a first direction; and second patterns disposed between the first patterns, and connecting the first patterns to each other in a second direction perpendicular to the first direction. The second patterns are arranged spaced apart from each other in the first direction, and arranged in a zigzag shape in the second direction.

A semiconductor device according to an embodiment includes a first stacked structure and a second stacked structure that are bonded to each other. The first stacked structure includes a first base body and a first connection structure disposed on a surface over the first base body. The second stacked structure includes a second base body and a second connection structure disposed on a surface over the second base body. Each of the first and second connection structures includes a connection pad, a carbon-based barrier layer disposed on the connection pad, and a bonding layer disposed on the carbon-based barrier layer and coupling the first and second connection structures to each other.

A semiconductor memory system includes a semiconductor memory device. The semiconductor memory device includes a first stack, a second stack, and a third stack. The second stack is disposed over the first stack. The second stack includes a plurality of word lines stacked and insulated from each other. The third stack is disposed over the second stack. The third stack includes a second selection line. The channel structure includes a first channel pillar formed through the first stack and the second stack, and a second channel pillar contacting the first channel pillar and formed in the third stack. A diameter of the second channel pillar is smaller than a diameter of the first channel pillar.

A memory device includes conductive patterns and first interlayer insulating layers stacked alternately with each other in a first direction, a dummy pattern separated from the conductive patterns in the first direction, a second interlayer insulating layer located between the conductive patterns and the dummy pattern, protruding patterns protruding in a second direction crossing the first direction from side surfaces of the first interlayer insulating layers and a side surface of the second interlayer insulating layer, and data storage patterns located between the protruding patterns.

A semiconductor device may include a first electrode, a second electrode, an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall, a variable resistance layer formed in the opening, the variable resistance including a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area, the variable resistance layer maintaining an amorphous state during a program operation, and a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode.