元の名称記録: Intel Corporation

Embodiments disclosed herein include an apparatus that comprises a substrate. In an embodiment, the substrate comprises a glass layer. In an embodiment, a frame is provided around a perimeter of the substrate. In an embodiment, the frame is over a top surface, a bottom surface, and a sidewall surface of the substrate. In an embodiment, the frame comprises a conductive material.

The present disclosure generally relates to a glass substrate comprising a glass core, a first buffer layer in contact with the glass core, a composite build-up layer incorporated in the first buffer layer, and an electrically conductive frame, wherein the first buffer layer, the composite build-up layer, and the electrically conductive frame, are peripherally disposed around the glass core. A method and a system are also disclosed.

According to the various aspects, a hybrid panel assembly includes an edge coated glass panel that is formed using a glass panel having peripheral edges and an adhesive coating layer deposited on the peripheral edges of the glass panel. The edge coated glass panel is a subcomponent for the construction of the hybrid panel assembly. A frame is provided to surround the edge coated glass panel and the adhesive coating layer bonds the frame to the glass panel to complete the construction of the hybrid panel assembly. In an aspect, the adhesive coating layer may be deposited by a coating roller and cured by a UV source.

Systems for cleaning bundles of fluid conduits include mechanisms for detecting and mapping fluid conduit locations as well as moving a cleaning device to the detected and mapped fluid conduit locations. Systems can clean the fluid conduits in a fluid conduit bundle, such as the fluid conduits of a heat exchanger.

The various aspects are directed to a two-phase jet impingement testing system having a water circulation system configured to convey pressurized heated water produced by a primary water heater and, optionally, by a secondary heater. A testing chamber is connected to the water circulation system, and the testing chamber includes a support for a device under test, a first inlet configured to introduce heated water from the primary water heater into the testing chamber, a second inlet configured to introduce a secondary heated water into the testing chamber to modulate the saturation pressure and temperature.

According to the various aspects, a testing probe may include an electrically conductive pad disposed on a substrate with an electrically conductive elastomer head disposed on the electrically conductive pad and a metal layer disposed on the electrically conductive elastomer head. In an aspect, a plurality of the testing probes are disposed on the substrate to form a probe head interposer.

In some embodiments, techniques for testing die to die interconnect links are provided.

In the various aspects, the present SoC package uses advanced die-to-die (D2D) interconnects having extra or spare lanes that, when any faulty lane(s) is uncovered during a dynamic HVM health check/testing phase, may be available as a substitute/replacement, or available for load sharing on a rotational basis. The present system and method also provide for an initial HVM health check, i.e., Sort/Class, that will include various tests to determine the working and non-working lanes of the D2D interconnects. In an aspect, when the SoC package is operational, i.e., in functional mode, the extra working lanes are not “fused” by the die-to-die interconnect IP. The present lane controller logic modules may be provided to check and change the lanes dynamically, i.e., as part of the dynamic health check, which can significantly help increase the lifetime of the whole SoC chips/package.

Apparatuses, methods and storage medium associated with compensating for a sensor deficiency in a heterogeneous sensor array are disclosed herein. In embodiments, an apparatus may include a compute device to aggregate perception data from individual perception pipelines, each of which is associated with respective one of different types of sensors of a heterogeneous sensor set, to identify a characteristic associated with a space to be monitored by the heterogeneous sensor set; detect a sensor deficiency associated with a first sensor of the sensors; and in response to a detection of the sensor deficiency, derive next perception data for more than one of the individual perception pipelines from sensor data originating from at least one second sensor of the sensors. Other embodiments may be disclosed or claimed.

The disclosure described herein generally relates to a system including one or more processors and one or more non-transitory computer-readable media storing instructions that, when executed by the one or more processors, cause the one or more processors to receive a first signal for spectral analysis wherein the first signal is a time division duplex (TDD) signal, apply a MUltiple SIgnal Classification-like (MUSIC-like) algorithm to the first signal to obtain one or more Doppler regions of interest, perform a high-resolution Doppler estimation utilizing Least Absolute Shrinkage and Selection Operator (LASSO) algorithm within the one or more Doppler regions of interest, and output a high-resolution Doppler spectrum for the first signal.

An apparatus including a memory and a processor configured to: obtain a range-Doppler periodogram of received sensing signals, wherein the range-Doppler periodogram is representative of one or more targets within a Doppler span; estimate a range-Doppler coordinate outside the Doppler span for the one or more targets; and selectively process a range-Doppler spectrum of the received sensing signals for the range-Doppler coordinate within a Doppler interval smaller than the Doppler span.

An optical connector, a semiconductor assembly including the optical connector, a multi-chip package including the optical connector, and a method of making the optical connector. The optical connector includes: a first lid; and a second lid attached to the first lid to define a cavity therebetween. Individual ones of the first lid and the second lid include: a substrate having an inner surface facing the cavity, an outer surface opposite the inner surface, a first end and a second end, the first end to receive a corresponding waveguide therein; and a concave mirror on the substrate and having a reflective surface facing the cavity, wherein a straight linear optical axis is to extend between the reflective surface of the concave mirror and a photonic structure at an opposing one of said individual ones of the first lid and the second lid.

Embodiments herein relate to a driver circuit for an optical modulator such as a micro-ring modulator (MRM). The driver circuit includes first and second drivers which receive respective differential data signals, and which have their output nodes coupled to a cathode and anode, respectively of the MRM. One or both of the drivers can have their output nodes alternating-current (AC)-coupled to a bias circuit which biases the voltage of the output signal to shift its voltage swing. The bias circuit can include a latch which receives Vbc_high at its power supply terminal and Vbc_low at its ground terminal, where Vbc_high>Vbc_low>0 V.

In some embodiments, bandgap reference circuits are provided that are capable of using PN junctions while transistors in the circuits can operate at reduced supply voltage levels.

The disclosure described herein generally relates to an apparatus, including: a Micro Controller Unit (MCU), configured to: monitor a working status of the apparatus; and communicate with an edge device when the edge device is connected with the apparatus; a Supercapacitor (SuperCAP) pack, configured to: discharge to supply power to the edge device when a power failure event occurs; and discharge to supply power to the edge device when a Central Processing Unit (CPU) of the edge device has a transient high peak current; a Buck-Boost voltage regulator controller, configured to drive a power stage MOSFET to regulate charging and discharging of the SuperCAP pack; and a power failure detection unit, configured to detect the power failure event.

Apparatus, devices, systems, methods, and articles of manufacture for intent-based machine programming are disclosed. An example system categorize source code blocks includes a code repository accessor to access a code repository and select a source code block. The example system also includes a signature generator to generate a signature for the source code block, a collateral miner to extract collateral associated with the source code block, and a tokenizer to transform the source code block into tokens. In addition, the example system includes a function assessor to determine a function of the source code block based on the collateral and the tokens and an input/output determiner to determine an input and an output of the source code block based on the collateral and the signature. The example system further includes a tagger to categorize the source code block with the function, input, and output.

A processor of an aspect includes a front end unit. The front end unit is to fetch and decode in parallel a first in-order sequence of instructions and a second in-order sequence of instructions. The first in-order sequence of instructions occurs before the second in-order sequence of instructions in program order. The processor also includes a back end unit coupled with the front end unit. The back end unit is to execute decoded instructions provided from the front end unit. Other processors, methods, systems, and instructions are disclosed.

An apparatus and method for improving the efficiency of sequences of load instructions. For example, one embodiment of a method comprises: storing, in one or more tracking structures of a memory operations circuit, information related to executed instances of a load instruction, including a loaded data value, a physical address from which the loaded data value was accessed, and a flag to be set to a first value when new instances of the load instruction are to be excluded from execution; detecting a first instance of the load instruction when the flag is set to the first value; and responsively replacing the first instance of the load instruction with a move instruction which, when executed, is to move the loaded data value from a first register to a destination architectural register indicated by the new load instruction.

Techniques for static instruction decoupling for data movement and computer are described. In some examples, hardware support at least includes a plurality of instruction queues to store instructions, wherein each instruction queue of the plurality of instruction queues is dedicated to a separate thread; a local memory to store instructions and/or data for a first thread; a scratchpad memory, coupled to the local memory, to store instructions and/or data for a second thread; and execution resources, coupled to the scratchpad memory, to execute one or more mathematic and/or logical instructions for a third thread.

Various examples relate to apparatuses, devices, methods, non-transitory computer-readable media and computer system for a first and a second virtual machine. A non-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries, cause the one or more processing circuitries to perform a method for a first virtual machine, with the method comprising executing an application, providing a virtual screen for a graphics output of the application, providing the graphics output provided to the virtual screen to a second virtual machine via an inter-virtual machine shared memory mechanism.