Memory Probing for Proactive Error Detection
Dossier Overview
Applicant
Arista Networks, Inc.
Inventor
Suhas Raghunath Joshi; Venkata Kishore Madhbhaktula; Rajnish Gupta
IPC Classification
CPC Classification
A network device may include data plane processing circuitry and memory circuitry accessible by the data plane processing circuitry to perform traffic processing operations. The memory circuitry may sometimes experience memory errors such as bit flips. One or more processors on the network device may access the memory circuitry, in parallel with the data plane processing circuitry accessing the memory circuitry, to detect and correct these memory errors more quickly, thereby reducing disruptions to traffic processing operations caused by memory errors.
Original (Chinese)
A network device may include data plane processing circuitry and memory circuitry accessible by the data plane processing circuitry to perform traffic processing operations. The memory circuitry may sometimes experience memory errors such as bit flips. One or more processors on the network device may access the memory circuitry, in parallel with the data plane processing circuitry accessing the memory circuitry, to detect and correct these memory errors more quickly, thereby reducing disruptions to traffic processing operations caused by memory errors.
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