REDUCING POWER CONSUMPTION OF NEURAL NETWORK ACCELERATOR THROUGH WEIGHT REORDERING

Original (Chinese)

To address the switching issue directly, an improved compiler can be implemented to prepare a DNN for hardware execution on a DNN accelerator in a way that considers switching activity during multiply accumulate (MAC) operations and reorders the weights to reduce the switching activity. The resulting compiled DNN can reduce energy consumption through reducing or minimizing switching activity in the DNN and can effectively reduce dynamic power consumption in DNN accelerators. The compiler can determine and enforce an improved weight ordering during the model compilation process. The compiler can be guided by one or more weight arrangement and reordering rules to ensure weights are ordered to minimize or reduce switching activity as much as possible without changing the output accuracy of the model or violating strict data paths of the MAC array. Compiled models with weight reordering would exhibit remarkably lower dynamic power consumption when deployed on DNN accelerators.